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Published in:   Vol. 7 Issue 1 Date of Publication:   June 2018

A Survey of Automatic Test Pattern Generation in BIST-VLSI

Giri Kuppusamy,Arunkumar Muthusamy

Page(s):   07-14 ISSN:   2278-2397
DOI:   10.20894/IJCNES. Publisher:   Integrated Intelligent Research (IIR)

Rapid improvement in VLSI field, it will open a new gate to the testing of the integrated circuits filed. In this literature paper we review collection of testing methods and all the testing procedures for integrated testing. The testing useful for hierarchical testing of large scale memory applications and stuck at fault detection schemes The DFT (design-for-test) tools seem to be running out of steam at various levels. To keep the parts on the tester for a longer time for more complex test runs by the ATE system. This is also other types of complex SoC devices. That seems to be the primary trend on the non-memory test front at the various levels. ATE suppliers because the test time starts to get longer VLSI Research doesnt have a specific market figure for MCUs, but it is believed to be in the hundreds of millions of dollars per year