DOI:10.20894/IJCNES.
Periodicity: Bi Annual.
Impact Factor:
SJIF:5.217
Submission:Any Time
Publisher:IIR Groups
Language:English
Review Process:
Double Blinded
The main objective is to detect the number of faults and to minimize the clock skew. Minimization of clock skew is quite difficult due to the PVT variations The post silicon skew tuning is the technique that has the ability to tolerate PVT variations (Process,Voltage and Temperature). Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. Unlike most previous works that have focused on the implementation and the performance issues of a PST architecture and it tells about one fault detection, this paper focuses on the testing issues of a PST architecture that detects more than one fault. However, testing the variation tolerance ability of the PST architecture is difficult because the clock skew does not directly affect the functionality of a design. In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we propose some novel structures to detect the manufacturing faults and increase the robustness of a PST architecture. Our experiment shows that with a little overhead, we can achieve robustness.
