Image compression is the application of Data compression on digital images. Two-Dimensional (2-D) discrete wavelet transform (DWT) is widely used in image and video compression. Lifting based and Convolution based designs have been suggested for efficient VLSI implementation of 2D-DWT. This paper presents an efficient implementation of high speed multiplier using the shift and adds method, Radix-8 modified Booth multiplier algorithm. The booth radix-8 multiplier reduces the number of the partial products, when compared to radix-4 booth multiplier. As a result of which they occupy lesser space as compared to the serial multiplier. Efficient area and low power 2D-DWT lifting is implemented. This is very important criteria because in the fabrication of chips and high performance system requires components which are as small as possible.