C. Cheng and K. K. Parhi, "High-speed VLSI implementation of 2D discrete wavelet transform", IEEE Transaction Signal Process ,Vol.56 ,2008 View Artical
C.-T. Huang, P.-C. Tseng and L.-G. Chen, "Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform", IEEE Transaction Signal Process ,Vol.52 ,2004 View Artical
B. K Y.-K. Lai, L.-F. Lien, and Y.-C. Shih,, "A high performance and memory-efficient VLSI architecture with parallel scanning method for 2D lifti", IEEE Transaction Consumption Electronics ,Vol.55 ,2009 View Artical
B.K. Mohanty, A. Mahajan, and P. K. Meher, "Area- and power-efficient architecture for high-throughput implementation of lifting 2-D DWT", IEEE Transaction Circuits System ,Vol.59 ,2012 View Artical
B. K. Mohanty and P. K. Meher, "Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT", IEEE Transaction Circuits System Video Technology ,Vol.23 ,2013 View Artical
B.-F. Wu and C.-F. Chung, "A high performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet t", IEEE Transaction Circuits System Video Technology ,Vol.15 ,Issue 12 ,2005 View Artical
G.-M. Shi, W.-F. Liu, L. Zhang, and F. Li,, "An efficient folded architecture for lifting-based discrete wavelet transform ,Vol.56 ,2009 View Artical
I.Daubechies and W. Sweldens, "Factoring wavelet transforms into lifting steps", J. Fourier Analysis and its Applications ,Vol.4 ,1998 View Artical
S.G.Mallat, "A theory for multiresolution signal decomposition: The wavelet representation", IEEE Transaction Pattern Analysis Machines Intelli ,Vol.11 ,1989 View Artical
W .Zhang, Z. Jiang, Z. Gao, and Y. Liu, "An efficient VLSI architecture for lifting-based discrete wavelet transform", IEEE Transaction Circuits System ,Vol.59 ,2012 View Artical
X. Tian, L. Wu, Y.-H. Tan, and J.W. Tian, "Efficient multi-input / multioutput VLSI architecture for two-dimensional lifting-based discrete 56 ", IEEE Transaction Computer ,Vol.60 ,2011 View Artical
Y.K. Lai, L.F. Lien, and Y.C. Shih, "A high-performance and memory efficient VLSI architecture with parallel scanning method for 2-D lift", IEEE Transaction Consumer Electronics ,Vol.55 ,2009 View Artical
